1. Field of the Invention
The present invention relates generally to timing structures and, more particularly, to delay and interpolation structures.
2. Description of the Related Art
A number of delay and interpolation timing structures have been proposed. For example, U.S. Pat. No. 5,081,380 to Chen couples switching transistors between a programmable current source and a capacitive load in the form of an MOS transistor. Timing delay is realized through the switching transistors which enable current mirrors coupled to the current source to source and sink currents to the MOS transistor. As a second example, U.S. Pat. No. 5,428,626 to Frisch et al discloses a timing analyzer that forms an interpolator with a string of serially-connected, voltage-controlled delay elements and a plurality of inverters and transmission gates that are coupled periodically along the string to provide delayed output signals. As a final example, U.S. Pat. No. 5,566,188 to Robbins, et al. combines a phase locked loop, a FIFO and numerous gates and registers to form an interpolator circuit.
Yet there remains a need for simple, inexpensive but precise delay and interpolation structures that are suitable for a variety of timing uses, e.g., generation and application of test signals by automatic test equipment (ATE) to devices under test (DUT). Preferably, these structures are configured to facilitate their realization as application specific integrated circuits (ASICs) to further reduce their size and cost when produced in large volumes.